A conventional technique for improving the performance of an integrated circuit containing insulated-gate FET's formed on a substrate is to provide a back bias voltage to the substrate at a suitable voltage level different from ground reference. This voltage level is negative for N-channel FET's and positive for P-channel FET's. The substrate bias voltage is typically generated on-chip with a circuit containing a charge pump.
S. Chen et al disclose such an on-chip circuit in "Feedback Substrate Bias Generator", IBM Technical Disclosure Bulletin, Vol. 23, No. 5, October, 1980, pp 1930-1. In this N-channel circuit, a ring oscillator provides an oscillating voltage to one input terminal of a two-input NOR gate whose output signal drives a single-stage charge pump which produces the substrate bias voltage. This is fed back to a capacitive voltage divider whose output controls a depletion-mode FET in an inverter. The output of the inverter is then supplied to the other input terminal of the NOR gate to provide closed-loop regulation of the bias voltage. More particularly, the input sections of the NOR gate consist of a pair of enhancement-mode FET's, one of which has its gate electrode connected to the drain of the depletion-mode FET for receiving the inverter output signal. When the bias voltage is above the threshold voltage of the depletion-mode FET, the inverter provides a logical "0" to the NOR gate so as to allow its output to change state at the ring oscillator frequency. This activates the charge pump which draws charge from the substrate to bring the bias voltage down to approximately the threshold voltage of the depletion-mode FET.
Chen et al indicate that their substrate bias generator compensates for temperature variations and can stabilize the bias voltage against chip-to-chip process variations that occur during integrated circuit fabrication. However, so stabilizing the bias voltage does not simultaneously act to significantly alleviate worst-case values for average gate propagation delay, power dissipation, and noise margin of metal-oxide semiconductor (MOS) FET static logic gates on the chips.
More specifically, MOS integrated circuit fabrication processes are conventionally characterized in terms of the four chip-to-chip processing corners commonly referred to as Fast Fast (FF), Fast Slow (FS), Slow Fast (SF), and Slow Slow (SS). The first word (letter) of each pair of words (letters) refers to the extreme parameters of enhancement-mode FET's, and the second word (letter) refers to the extreme parameters of depletion-mode FET's. The range from Slow to Fast for one of the types of FET's thus refers to the spread in performance from chip-to-chip for that particular type of FET. FET's operate at the greatest speed in the Fast condition while the converse is true for the Slow condition.
Processing variations and variations in operating conditions such as drain supply voltage and chip temperature often produce wide differences in gate performance. Typically, the chip-to-chip spread in average gate propagation delay is 300-400 percent at the same temperature and drain supply voltage. The spread in average gate power dissipation is slightly less.
The difficulty in insuring that worst-case propagation delay, power dissipation, and noise margin do not go beyond prescribed specification limits is that these worst-case parameters do not all occur at the same corner of the processing range or at the same end of the operating conditions. The greatest propagation delay occurs at the SS corner at maximum temperature and maximum drain supply voltage. The greatest power dissipation occurs at the FF corner at minumum temperature and maximum supply voltage. Power dissipation is, however, most critical at high temperature. The noise margin is lowest at the FF corner at minimum supply voltage and maximum temperature.
Consideration has been given to a substrate bias generator in which the bias voltage is varied in such a manner as to stabilize the average gate propagation delay of a string of NOR gates that form an oscillator. This technique, however, does not provide a desirable noise margin profile across the FET processing range.